The invention pertains generally to the field of power conversion, and more particularly to digitally-controlled switched-mode DC/DC converters.
A broad class of switched-mode DC/DC power converters exists with the property that the ratio of the average output voltage to the input voltage is determined by the average duty cycle of a controllable switching device within the power conversion stage of the converter. Examples include buck, boost, inverting buck-boost, forward, and flyback converters, operated in the continuous conduction mode (CCM). Where the load on the power converter is steady, or there is no requirement to track changes in load with minimal output voltage error, regulation of these converters is accomplished by continually estimating the target duty cycle (the target duty cycle being the duty cycle essential to achieve the desired output voltage) and continually adjusting the duty cycle of the switching device to track target duty cycle estimates. In this case, the act of regulation consists of controlling, cycle by cycle, the duty cycle of the switching device in accordance with target duty cycle estimates, so that the average output voltage is equivalent to the desired output voltage.
Regulation mechanisms for this purpose generally incorporate a pulse width modulation (PWM) mechanism and a target duty cycle estimation mechanism, where the former generates an ON pulse appropriate to the realization of the target duty cycle estimate generated by the latter. The target duty cycle estimation mechanism is typically a feedback mechanism, driven by the output voltage error, but it could as well be a feedforward mechanism, driven by the input voltage, or it could be some combination of the two.
The most commonly used PWM mechanisms are analog in nature; that is they accept as input a continuously variable analog signal representing the desired duty cycle, and they output pulses of continuously variable width. As in other previously analog fields, continuous advances in integrated circuit technology have stimulated the application of digital techniques to the field of power conversion. As a result, the first digital regulation mechanisms, replacing analog PWM mechanisms, have been developed and are being commercialized. It is the nature of such mechanisms that the generated pulse widths are quantized—a consequence of the temporal resolution of the digital regulation mechanism. If the temporal resolution of the regulation mechanism is Δt, then the pulse widths are constrained to be integral multiples of Δt. Furthermore, switching cycles, spanning consecutive ON and OFF pulses, are likewise constrained to be integral multiples of Δt.
One challenge to those who would apply digital regulation mechanisms to power converters, especially DC/DC converters employed in battery-powered mobile applications, is the challenge of achieving acceptable application performance with digital regulation mechanisms. Quantization of pulse widths translates into quantized duty cycles, which typically translates into a requirement for a sequencing mechanism to realize, via time-averaging, the duty cycle precision essential to achieve the desired output voltage. This requirement, in itself, presents an implementation challenge to designers of digital duty cycle regulation mechanisms; a number of practical solutions may be found in the prior art (cf. U.S. Pat. No. 5,272,614 and U.S. Pat. No. 5,886,513). It remains, however, to mitigate the effects of quantization on application performance.
To understand the nature of this challenge, consider a DC/DC converter in a battery powered mobile application. The switching frequency is typically set in the neighborhood of 1 MHz, to minimize the size and cost of discrete components and maximize the operating efficiency of the converter. A digital regulation mechanism operating at 16 MHz would be able to generate pulses widths of 0, 1/16 usec, 2/16 usec, 3/16 usec . . . 16/16 usec. Assuming a fixed switching frequency, 17 instantaneous duty cycles (including 0 and 1) could be applied. One method for time-averaging to a target duty cycle would be to construct a sequence comprised of two quantized duty cycles, one smaller than the target duty cycle, and the other larger. Two distinct embodiments of this concept can be found in the prior art (cf. U.S. Pat. No. 5,272,614 and U.S. Pat. No. 5,886,513). In each case, the sequencing mechanism constructs, from a set of two quantized duty cycles, a sequencing pattern appropriate to realize, via time-averaging, the estimated target duty cycle. At their best, however, these sequencing mechanisms may not be able to limit output voltage ripple to an acceptable level . . . in which case the only obvious recourse for manufacturers of regulators is to improve the temporal resolution of the digital regulation mechanism . . . i.e., boost the clock frequency.
But boosting the clock frequency to mitigate the effects of quantization on output voltage ripple may compromise cost and efficiency metrics. For example, the complexity and, consequently, the cost of the digital regulation mechanism are likely to increase as well as the power dissipation. Moreover, the increased cost and power dissipation would be further multiplied, if the requirement to boost the clock frequency should prevent the integration (at a substrate level) of the digital regulation mechanism with other electronic componentry.
Clearly there is a need for digital control methods that mitigate the requirement for higher clock frequencies solely for the purpose of achieving acceptable output voltage ripple in a broad class of DC/DC converters.